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Appendix B: Python → Rust Idiom Translations

For readers coming from cocotb and pyuvm (and Python for RTL Verification): the working translations this book used, gathered for reference. SystemVerilog readers want Appendix C, this table’s twin. Legend: [C] cocotb, [P] pyuvm.

Language and runtime

PythonRustChapter
async def coroutine, resumed via send(None)async fn → Future, resumed via poll()15
@cocotb.test()#[rustdv::test]15, 21
exceptions fail the testResult<(), TestError>; panics = testbench bugs9, 18
cocotb.start_soon(coro)spawn(future) -> TaskHandle<T>16
await tasktask.await → Result<T, TaskError>16
task.kill()handle.cancel() — the future is dropped; cleanup in Drop16
Combine(...) / First(...)join2/join! / first2/first!16
try/except QueueFulltry_put → Result<(), T> (rejected item handed back)16, 31
decorator registration at import timelink-section registration at compile time21
metaclass class registrationnot needed — constructor injection21, 29
getattr(obj, name) dispatchpass the function/closure itself33
logging levels + handlerslog:: levels, set_level_for(prefix), log_to_file26

cocotb layer

Python (cocotb)Rust (rustdv-sim)Chapter
Timer(2, units="ns")Timer::ns(2).await15
RisingEdge(sig) / FallingEdge(sig)sig.rising_edge().await / sig.falling_edge().await17
ClockCycles(clk, n)for _ in 0..n { clk.rising_edge().await; }17
dut.sig attribute magicdut.signal("sig")? → Result<LogicHandle, _>17
sig.value = x / int(sig.value)sig.set_u64(x) / sig.get_u64()?17
Clock(dut.clk, 10, units="ns").start()Clock::new(&clk, SimDuration::ns(10)).start()17
cocotb.queue.Queue(maxsize=1)Queue::new(Some(1)); Queue::unbounded()16
Event / Locksim::Event / sim::Lock (FIFO-fair, RAII guard)16

pyuvm layer

Python (pyuvm)Rust (rustdv)Chapter
@pyuvm.test() on a class, uvm_test_top#[rustdv::test] on a struct; the root is named after your test23
raise_objection()/drop_objection()ctx.raise_objection(..) → RAII ObjectionGuard; drop releases23
uvm_component(name, parent) treechildren are struct fields; #[derive(Component)]; paths derived24
the nine phases, pyuvm’s traversal orderthe nine phases, same order: build, connect, … final_phase24
self.logger, [uvm_test_top.comp]ctx.info(..), same bracket format, path supplied by the walk26
ConfigDB().set/get, wildcards, globalsConfigDb::set/get — same paths, same globs, Result answers25, 27
except UVMConfigItemNotFoundmatch on ConfigError::NotFound { .. }28
metaclass registration + create()#[derive(Component)] registers; Foo::create_comp()21, 29
set_type_override_by_typeFactory::set_type_override::<A, B>() (also by name, by instance)29, 30
TLM-1 put/get/peek port classesPutPort/GetPort/PeekPort, wired export-to-port through a TlmFifo31
UVMTLMConnectionError (lazy, at first use)elaboration sweep names every unwired port before run31
uvm_analysis_port.write()PublishPort<T>::write(&T) through an AnalysisBus hub32
uvm_subscriber (one write per class)a Subscriber<T> impl per stream — two streams, two impls32, 34
uvm_tlm_analysis_fifoabsent — the subscriber owns its storage32
uvm_object do_copy/do_compare/__str__#[derive(Clone, PartialEq, Debug)] + hand-written Display35
copy(other) / clone()clone_from(&mut self, src) / clone()35
uvm_sequence.body()impl Sequence — type Req/type Rsp, async fn body(ctx)36
start_item/finish_itemctx.start_item(&mut req) / ctx.finish_item(req) → ticket36
seq_item_port.get_next_item()port.get_next_item().await → SeqItem<REQ>36
item_done() / item_done(rsp) + set_id_infoitem_done(None) / item_done(Some(rsp)) — auto-tagged36, 38
get_response()get_response(Some(ticket)) / try_get_response — in order or by ticket37, 38
(no pyuvm counterpart) try_next_itemtry_next_item() → Option — the UVM’s non-blocking accept, kept37
seq.start(seqr) / start(None) for virtualseq.start(&seqr) / start_virtual()36, 39
is_active int from ConfigDBActive enum from the ConfigDb; a passive env skips building the driver40