rustdv: The UVM in Rust
try it, then come discuss it
The UVM, transformed to run in Rust: the component tree and its phases, the ConfigDb, the factory, TLM, analysis, and the full sequencer handshake. Your testbench compiles to native code that the simulator loads. Zero external dependencies.
What it looks like
A rustdv test is an async Rust function. Signals are handles
you read and drive; simulated time is something you await.
use rustdv::prelude::*;
rustdv::vpi_bootstrap!();
#[rustdv::test]
async fn alu_test(ctx: RustdvCtx) -> Result<(), TestError> {
// Reset the DUT
let dut = ctx.dut();
let clk = dut.signal("clk")?;
let reset_n = dut.signal("reset_n")?;
let start = dut.signal("start")?;
clk.falling_edge().await;
reset_n.set_u64(0);
start.set_u64(0);
clk.falling_edge().await;
reset_n.set_u64(1);
// ... drive transactions, check results ...
Ok(())
}Abridged from the book's testbench 1.0 — in the book itself, every listing is real code from a runnable example, and every transcript is genuine Icarus Verilog output.
From cargo build to REGRESSION: PASS
A rustdv testbench keeps the shape a UVM engineer knows — a tree of components walked by the nine phases. What changes is what it compiles to.
A testbench is a crate
Tests, environments, agents, and sequences are Rust structs and traits —
#[derive(Component)] writes the tree plumbing. One
cargo build turns the whole testbench into a single native
library. If it built, it runs.
rustdv drives the top module
The simulator loads that library and hands rustdv the DUT. There is no Verilog testbench at all — no harness module, no DPI shims, nothing to keep in sync on the HDL side.
The phases walk the tree
Top-down build, bottom-up connect, an elaboration
sweep that names every unwired port — then a concurrent run that
ends when the last objection drops, and the closing phases where the
scoreboard has its say.
The run ends in a verdict
Every run closes with the regression table and
REGRESSION: PASS — or a failing test, a named cause, and a
nonzero exit code your CI can act on.
Why rustdv
The methodology you know
The component tree with build and connect phases, path-addressed configuration, factory overrides by type, name, or instance, TLM ports and FIFOs, analysis ports and subscribers, and the complete sequencer handshake — including virtual sequences. Inspired by the UVM, rebuilt with Rust's own tools.
Unit tests without a simulator
rustdv components are ordinary Rust structs. Predictors, transaction
operations, and coverage logic run under cargo test in
milliseconds — no simulator license anywhere in sight.
Native speed
Rust compiles to the same kind of native code as the simulator itself, with no interpreter and no garbage collector in the loop. For regression farms running thousands of seeds — or testbenches that must keep up with an emulator — testbench overhead is real money and real schedule.
A compiler that earns its keep
Transactions are plain structs the compiler knows field by field: rename one, and it lists every place that must change. Every object has exactly one owner, which settles at compile time a question methodologies otherwise answer with convention and code review.
An open toolchain, end to end
The Rust compiler, cargo, the crates.io ecosystem, and rustdv itself are free and open source. With Icarus Verilog as the simulator, the entire flow — from first chapter to passing regression — costs nothing.
Verified, not aspirational
The shipped TinyALU testbench ends REGRESSION: PASS, and the
checking has teeth: corrupt the DUT's XOR into an OR, and the scoreboard flags
every affected transaction. Every claim on this site is backed by a test that
runs.
Learn it from the book
Rust for RTL Verification is rustdv's companion book — the third in Ray Salemi's series after The UVM Primer (SystemVerilog) and Python for RTL Verification (Python). It assumes no prior Rust: forty chapters teach the language from zero, then rebuild the TinyALU testbench version by version, 1.0 through 8.0, adding one UVM capability at a time.
Every figure runs. Every simulation transcript is genuine Icarus Verilog output, kept in sync with the code by the project's regression suite.
Where rustdv stands
The framework is complete and verified: a regression suite gates every push, every figure in the book's forty chapters runs, and the checking itself is mutation-tested. What rustdv becomes next — which features, which simulators, which direction — is an open question, and it should be answered in the open. The discussion is the front door, and issues and pull requests are open behind it. Try rustdv on something real, then come say what happened — that is exactly how Verilator support arrived.
rustdv was created by Ray Salemi — author of The UVM Primer and creator of pyuvm — working with Claude, as an example of level-5 software development. The story →