Introduction to rustdv

What rustdv is, and a complete reference for what it provides.

The UVM

The Universal Verification Methodology (UVM) is the dominant RTL verification methodology across the IC industry. The UVM is popular because it allows engineers to reuse testbench components across testbenches, and because it provides a standardized testbench structure that engineers recognize as they move across projects, companies, and industries. If you apply for a job as a verification engineer, it is likely that the hiring team uses the UVM and will test your UVM knowledge.

IEEE defined the UVM in the IEEE Standard for Universal Verification Methodology Language Reference Manual, also known as the IEEE 1800.2 standard. While the industry defined the standard in terms of SystemVerilog, the methodology's ideas travel: pyuvm implements it in Python (on top of cocotb), and rustdv brings those same ideas to Rust.

What rustdv is

rustdv is a hardware verification framework inspired by the UVM. It is not an implementation of IEEE 1800.2 — the standard is written in terms of object-oriented class hierarchies, and Rust is not an object-oriented language — and some layers, notably TLM and the analysis layer, are deliberately done differently. What rustdv takes from the UVM is what makes the UVM valuable: the testbench structure, the phased component tree, late binding through configuration and a factory, and the sequence machinery, re-created with Rust's own tools — structs, traits, and ownership.

Where the Python story needs two projects — cocotb to talk to the simulator and pyuvm to provide the methodology — rustdv contains both layers: a simulator-driven async executor with triggers and signal handles underneath, and the component methodology on top. Testbenches compile to native shared libraries that the simulator loads over VPI, with zero external dependencies. The examples and the regression suite run on Icarus Verilog, which is free and open source.

The methodology layer provides the UVM structure a verification engineer expects:

• A component tree with the nine UVM phases, in the UVM's traversal order — top-down build, bottom-up connect, a concurrent, objection-gated run, and the closing phases.
• Path-addressed runtime configuration (ConfigDb) with the UVM's wildcard paths — and a Result answer that names the cause when a lookup fails.
• A factory with overrides by type, by name, and by instance, for both components and sequences.
• TLM ports, exports, and FIFOs — two components connect to the same FIFO and neither learns the other exists.
• Analysis ports and subscribers for monitors, scoreboards, and coverage.
• The full sequencer handshake — start_item/finish_item, get_next_item/item_done, responses in order or by ticket, and virtual sequences.
• UVM-style logging with per-hierarchy verbosity control and the familiar time/level/path line format.

Because rustdv components are ordinary Rust structs, the pure-software parts of a testbench — predictors, transaction operations, coverage logic — also run under cargo test with no simulator at all.

Getting started

The Getting Started page takes you from an empty directory to a running testbench in three small files, then to the complete TinyALU testbench the repository ships.

The companion book, Rust for RTL Verification, is the front door to the methodology. It assumes no prior Rust — the first fourteen chapters teach the language from zero — and then builds a complete TinyALU testbench version by version, adding one UVM capability at a time. The Interlude shows the complete testbench in one place and is the best single answer to “what does rustdv code look like?”

The framework lives at github.com/rustdv/rustdv and is published as rustdv on crates.io. Questions and discussion belong in GitHub Discussions.

What rustdv provides

Every rustdv listing in the book opens with use rustdv::prelude::* — the analog of import uvm_pkg::* and from pyuvm import *. The tables below are the complete reference for what that line brings into scope, plus the macros. The Chapter column points to where the book teaches each name; a dash means the name is provided for completeness but the book's examples never need it.

The prelude, alphabetically

The macros

On the surface, outside the prelude

A few names live on the crate but not in the prelude; reach them as rustdv::Name.

The whole of each layer is also re-exported for power users: rustdv::sim, rustdv::runner, rustdv::gpi.